The invention relates to analog-to-digital conversion circuits, and more particularly to a high speed analog-to-digital conversion circuit using a massively parallel analog-to-digital conversion technique.
Analog-to-digital conversion (ADC) is performed to convert an analog signal to a digital number indicative of the amplitude of the analog signal. The digital number is typically digital code in 4-bit to 10-bit depending on the precision of the conversion. Analog-to-digital conversion is performed by sampling the analog signal at a predetermined frequency and converting the amplitude of the sampled signal to a digital number representative of the amplitude. The speeds of the analog-to-digital conversion typically range from 15 to 300 megasamples per second (MSPS). To accurately represent an analog signal in digital form, the analog signal must be sampled at at least twice the highest frequency present in the analog signal. Therefore, for a high frequency signal, such as a 200 MHz analog signal, the speed of the ADC conversion must be at least 400 MSPS to provide an accurate representation.
Analog-to-digital conversion is commonly used in applications such as audio signal processing, video and medical imaging and high speed communications. The analog signals are converted to digital representations so that subsequent digital signal processing (DSP) techniques can be applied to the digital data. DSP techniques for processing digital data can include data compression, noise filtering, data storage, noiseless transmission of data, and digital encryption of data.
For applications operating at very high frequency or very high transmission rate, a high speed (e.g. 400 MSPS) analog-to-digital (A/D) converter is needed to ensure accurate conversion. Such high speed A/D converters are typically very complex and complicated to design. A single-chip high speed A/D converter can be quite large and can consume large amount of power in operation. It is desirable to provide a high speed A/D converter that is smaller and simple to design so that power consumption and manufacturing cost can be reduced.
In accordance with one embodiment of the present invention, a circuit includes an input terminal coupled to receive an analog input signal, a multiple number of sample-and-hold circuits and a multiple number of analog-to-digital (A/D) converters. The input terminal of each of the sample-and-hold circuits is coupled to the input terminal of the circuit receiving the analog input signal. Each of the A/D converters has an input terminal and an output terminal, where the input terminal is coupled to an output terminal of a corresponding one of the sample-and-hold circuits. In operation, the sample-and-hold circuits sample the analog input signal sequentially and store a multiple number of analog samples at each of the sample-and-hold circuits. The A/D converters convert the analog samples in parallel to generate digital values at the output terminals of each of the A/D converters representative of the analog samples.
In one embodiment, the A/D converters are implemented based on a multi-channel bit-serial (MCBS) analog-to-digital conversion scheme. Each A/D converter includes a comparator receiving a first signal having a number of levels and a latch receiving and a series of binary signals. The A/D converter operates to convert the analog sample to a digital code representation.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.